The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a recess pattern in a semiconductor device.
Presently, semiconductor devices have become highly integrated. In a method for forming a typical planar gate in which a gate is formed over a planarized active region, a gate channel length is decreased and an ion implantation doping concentration is increased. Thus, a junction leakage current is generated by an increased electric field. As a result, it has become difficult to secure a refresh characteristic of a device.
To overcome aforementioned limitations, a recess gate process is performed. The recess gate process includes a gate line formation method in which an active region of a substrate is etched into a recess pattern and subsequently, a gate is formed. Using the recess gate process reduces the channel length increase and the ion implantation doping concentration. Thus, the refresh characteristic is improved.
FIG. 1 illustrates a micrographic view of a typical recess pattern in a semiconductor device. An isolation structure 12 is formed in a substrate 11 to define active regions. The active regions are formed in a direction along a major axis. The active regions include line type recess patterns 14 formed in a direction along a minor axis. A method for forming the recess patterns 14 is described in FIGS. 2A to 2C.
FIGS. 2A to 2C illustrate cross-sectional views of a typical method for fabricating a recess pattern in a semiconductor device. The same or like reference numerals used for the descriptions in FIG. 1, FIGS. 2A to 2C, and FIG. 3 represent the same or like elements for convenience of description.
Referring to FIG. 2A, an isolation structure 12 is formed in a substrate 11 to define an active region. A mask pattern 13 is formed over the resultant structure, the mask pattern 13 exposing recess pattern regions. The mask pattern 13 is formed in a line type structure. The mask pattern 13 is formed over the substrate 11 with a uniform spacing distance. The mask pattern 13 is formed over the isolation structure 12 as well as the active region.
Referring to FIG. 2B, the substrate 11 is etched using the mask pattern 13 as an etch mask to form recess patterns 14. Reference numeral 12A refers to a remaining isolation structure 12A.
Referring to FIG. 2C, a gate insulation layer 15 is formed over the surface profile of the resultant structure. Gate patterns are then formed in a manner that a portion of the gate patterns is filled in the recess patterns 14 and the rest of the gate patterns protrude above the substrate 11. Each gate pattern includes a stack structure configured with a gate electrode 16 and a gate hard mask 17.
In the typical method, the recess patterns 14 are formed over both the isolation structure 12 and the active region of the substrate 11. A gate line width has decreased to 70 nm or smaller as the design rule decreases. Thus, patterning for securing a small space of 40 nm or smaller is often required.
The typical method forms the recess patterns 14 in a small space, and thus, a portion of the substrate 11 adjacent to the isolation structure 12 may be damaged (as shown with reference numeral 100 in FIG. 1). Consequently, a coupling 200 results between the active region and the gate pattern. A cell transistor may not operate due to the coupling 200. FIG. 3 illustrates a micrographic view of the coupling 200 generated during the typical method for forming the recess pattern in the semiconductor device.
Furthermore, it may be difficult to embody a pattern having a small width, e.g., ranging from 20 nm to 40 nm, due to a lack of resolution of a photoresist pattern. Such a limitation causes a device process to become more difficult to perform and diminishes mass producibility due to the decreased process margin.